ATD WEB SITE FAQ
Question: Why consider custom integration?
There are a number of reasons why developing a custom Integrated Circuit is an appropriate and often essential ingredient to the development of a successful product:
1. Size. The continued market demand to reduce the size of electronic devices, in particular portable and hand-held devices, requires ever higher levels of integration. Replacing functions requiring the use of a number of discrete components with one IC helps achieve this goal.
2. Performance. By utilizing the superior matching and tracking characteristics of integrated circuit components, manual adjustment of circuit parameters can often be eliminated, while maintaining tighter spread on key system performance specs over the full range of operating conditions. Additionally, critical or high-precision specs can be trimmed at wafer test.
3. Cost. Replacing a number of discrete components with a pre-tested IC significantly reduces the test time and the number of rejects. For large production quantities the initial development cost will be amortized in a short period of time, resulting in a lower cost per unit.
4. Reliability. An IC is significantly more reliable than a PCB populated with the devices necessary to provide the equivalent functionality using discrete components or multiple IC's.
5. Copy protection. This can be the most important incentive to consider custom integration. Simple hardware copying is prevented because of the exclusivity of the custom IC.
Question: What information is necessary for starting the design of a custom IC?
There are several possible approaches to specifying a custom integrated circuit, some of which are listed below:
1. Specification in Data Sheet Format
This is an ideal starting point. However, since it requires a high level of understanding of the capabilities and limitations of integrated circuit technology, it is often beyond the capabilities of a customer without an internal IC design or product definition group.2. Specification Based on Existing Implementation
The schematic of the existing system together with a shortlist of key performance and critical specification requirements is usually an adequate starting point.3. Specification Based on Theoretical System Design
A detailed specification of the function(s) to be integrated is required, together with the system-level schematic.4. Specification Based on Functional Description
Part of the initial design phase will involve the building of a detailed chip-level specification from a higher level functional description.5. Specification Based on Feasibility Study
This is appropriate when it is not clear to what degree some aspects of device performance can be achieved using currently available technology options.
The amount of initial design effort is different for each possible scenario, since all approaches have to be expanded and refined to the common level of a data sheet specification before detailed circuit design can commence.
Question: What are some of the main differences between system-level and IC design?
Both system-level and IC design methodologies are based broadly on the same fundamental circuit concepts. However, there are usually significant differences in how each methodology achieves equivalent functionality at the detailed level. With the possible exception of IC design approaches based on standard cell libraries, most IC design is performed at the transistor level. IC design methods rely heavily on circuit approaches which emphasize the excellent matching performance of integrated components, while de-emphasizing their generally looser absolute tolerances and poorer thermal characteristics. There are many elegant and/or high performance circuit solutions which rely on extremely close component matching, and which are therefore only suitable for implementation on an IC. In addition, there are many design considerations which are unique to IC design. For example, close attention has to be paid to parasitic devices, formed as a by-product of monolithic IC fabrication methods, to avoid unexpected results such as degraded performance or critical malfunction of the physical circuit. Careful consideration has to be given to reliability issues such as ESD and electromigration. The use of large value resistors or capacitors is generally not an option, unless employed as external components. Resistors, in general, are avoided as far as possible by the use of current mirrors and other current-mode circuit design techniques. Every instance of the use of negative feedback has to be assessed for stability, and optimized to use the smallest possible amount of dedicated compensation capacitance. Due to the often limited number of externally accessible circuit nodes, design-for-testability issues are usually much more demanding than for system-level implementations. Perhaps one of the biggest differences between system-level design and present-day IC design methods is the almost total replacement of breadboarding by computer simulation
Question: What are the technology options?
The three principal technologies which are readily accessible for custom integration are Biploar, CMOS and BiCMOS. The following is a somewhat simplified overview of their relative strengths and weaknesses. For analog circuits, bipolar technology is generally the most suitable, as it provides the widest range of options for implementing many different types of circuit functions. It is also capable of operating at extremely high frequencies, and provides the lowest noise figure. BiCMOS technology is appropriate for circuits containing both analog and logic functions, particularly where the analog functionality would be difficult to achieve in CMOS technology, and where the logic section does not require a high packing density. It attempts to combine the best of both technologies, but in general the analog qualities of the bipolar devices and the density of the CMOS devices are inferior to those of comparable dedicated processes. Also, due to the extra mask levels involved, BiCMOS technology is usually a little more expensive. CMOS is best suited for dense logic circuits. Since most CMOS processes are optimized to achieve the smallest geometry logic-grade transistor, analog performance usually suffers. Combined analog and logic circuits can, however, be implemented on both bipolar and CMOS technologies, but logic circuits implemented on bipolar technology are generally wasteful of silicon area and power, and analog circuits implemented on CMOS technology generally cannot achieve the same levels of performance and/or precision as bipolar technology. These are some of the compromises which need to be addressed when choosing the technology which is most appropriate for any given set of requirements.
Another technology option is the choice between using a prefabricated semi-custom array or undertaking a full custom development. Semi-custom arrays consist of ready-made devices: transistors; fixed value resistors; and usually a few capacitors and diodes. Functionality is defined using one or more metal interconnect layers. Silicon foundries usually keep a stock of the arrays they support in the form of "mirrors" (i.e. wafers completed up to first metallization, and held prior to patterning of the first interconnect layer). The only processing steps involve interconnect and passivation layers - just two layers for single level metal interconnect. The main advantages of the semi-custom solution is lower engineering costs, faster turnaround of both the prototyping and production phases, and relative ease and low cost of implementing revisions. The main disadvantages are a die size which is usually between 20% and 100% larger than could be achieved using a full-custom layout approach, and the inability to change device geometries to achieve optimal circuit performance. Semi-custom may be the only viable option if production quantities do not meet foundry requirements for accepting a full custom production commitment. Examples of both approaches are shown below:
Small Section of a Semi-custom Base Array Without Interconnect
Section of Semi-custom Array with Single Level Metal Interconnect
Small Section of a Typical Full Custom Layout
Question: What are the costs involved in developing a custom IC?
The NRE (Non Recurring Engineering) costs consist of Design Fees and Production Engineering Fees. The Design fees depend on the complexity of the project and how stringent the performance requirements are. In general, full custom designs require more engineering time than semi-custom designs. Design fees are set based on estimates of the engineer/weeks required to complete the project. Production Engineering costs vary widely from foundry to foundry and are higher for full custom implementations. There is also a sensitivity to production quantities, tending to be more expensive for lower quantities.
Design fees range between US$40,000 and US$80,000. Production Engineering fees range between US$10,000 and US$40,000.
Question: How long does it take to develop a custom IC?
A proprietary IC development consists of two major steps: Design, and Production Engineering Setup. Typical design cycles range from 10 to 18 weeks. In general, full custom implementation takes longer than semi-custom. Production Engineering setup can take 3 to 6 weeks, after which prototypes are available. After approval of prototypes it can take another 2 to 4 weeks for production test setup. This is also subject to internal scheduling.
Question: What are ATD's areas of expertise?
Video Broadcast Technology
Sync regeneration
Noise immune back porch clamping
Sync tip clamping (hard and soft)
Synchronizing Generators
Pulse shaping techniques
Camera signal conditioning
Digital Communications
Clock acquisition
Bit regeneration
Multilevel (Duo-binary) encoding/decoding
Passive phase correction
RF microwave design
Digital Video
Adaptive Cable Equalization (up to 1.5Gb)
C lock acquisition
Bit regeneration
Automatic standards detection
De-serialization (to >2Gb/s)
Cable simulator networks
Power Management
Linear and switching power supplies
Synchronous battery chargers
Precision voltage references
Hot-swap controllers
General Physics
Gamma radiation Detection
Element Identification and Quantitative Measurement
Industrial metal detection
Proprietary Software
Simulation enhancement program (SONIC - Spice Oriented Netlist Interface Control program)
- Provides the capability to e.g. automatically generate layout parasitic devices, with particular emphasis on parasitic structures which affect high frequency simulation accuracy.
- Facilitates efficient design re-use by allowing schematics to be largely technology independent.
- Built-in macro-modeling algorithm for short transmission lines - oriented to high speed full system simulations of CHIP + PACKAGE + PCB
